View GT-6816_391591.PDF datasheet online --- IC-ON-LINE

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I. General Descriptions-
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ethigh-performance color scanner. The GT-6816 is enhanced not only in the AFE (SOC) solution for heEnd) from 12-bit to 16-bit but also built-in an intelligent power management circuit to (Analog S Front a operating and suspend mode for USB bus-powered Scanner. The GT-6816 is also pin to pin meettboth a backward D compatible with the GT-6801, providing system designer easy way to upgrade the current .
applications without changing the hardware design. II. Features
The GT-6816 is an enhanced version of GT-6801, which provides highly integrated System-On-Chip
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GT-6816
Single-chip integration for high-performance color scanner application On-chip Analog Front End: CDS/AGC and 16-bit ADC Maximum 6MHz On-chip universal TG supports various types of CCD/CIS sensors Embedded high-performance RISC controller On-chip USB transceiver Built-in 16KB image line buffers PC interface supports : USB/EPP/ECP/BPP No external memory component required for typical application Firmware programmable frame size Intelligent power management meets both operating and suspend mode for USB bus power On-chip PLL circuits Operating clock :48 MHz with external crystal: 6 MHz Operating voltage: Core: 3.3V I/O: 5V , Operating current: Core 80mA, AFE 50mA Suspend current: 50 A Package: 128-QFP & 44-QFP
AFE
CDS
6 MHz Crystal
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DRIVER
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I/O
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PGA
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16-bit ADC
Compression Engine
PLL
Universal Timing Generator
Scanner Control Logic
Image Buffer
PC interface
Parallel port ECP
MOTOR
RISC
Program memory
Mask ROM
EPP
Intelligent Power Management
SPP
USB
ROM 2KB
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GT-6816
III. Benefits
Provides a total solution, fast time-to-market USB bus power without additional power line Supports a wide range of applications Customer differentiation via firmware Provides firmware update path via USB channel Easy to meet EMI standard Minimum external components Supports a full set of development kit Single chip solution, stock management becomes easier
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IV. Pin Configuration-
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
MA0 MA1 GND MA2 MA3 MA4 MA5 MA6 VDD MA7 MA8 MA9 MA10 MA11 GNDI MA12 MA13 MA14 MA15 AFEEN VDDI MD0 MD1 MD2 MD3 MD4
1 2 3 4 5 6 7 8 9 10 11 H2 H1 VDD1 X1 X2 GND1 RS WAKEUP TGB TGG TGR
12 13 14 15 16 17 18 19 20 21 22 RST GPIO5 GPIO6 GPIO7 GNDI1 PD0 PD1 PD2 PD3 VDDI1 SDA
SHB SHS NC2 VDDI2 GNDI2 VDD2 GND2 VDDA2 VR VG NC1 VB VCM VRT VRB GNDA VDDA1 VDDU D+ DGNDU SCL
44 43 42 41 40 39 38 37 36 35 34
Type(A)- 44-pin QFP
33 32 31 30 29 28 27 26 25 24 23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 VDDA VR VG VB GNDA VCM VRT VRB GNDA NC1 GNDA VOUTP VDDA VOUTM VDDA NC2 VDDU USBDP USBDM GNDU USBEN TEST SCL SDA GNDI WDTEN HSTRB HAFD GNDI HINIT HSLCIN HPE VDDI HSLC HERR HACK VDDI HBUSY
MD5 SHS MD6 GND SHB MD7 OE WE H2 PORT0 PORT1 H1 VDD PORT2 PORT3 PLLEN VDDP X1 X2 GNDP GND GPIO1 GPIO2 GPIO3 GND RS PORT4 WAKEUP PORT5 TGB PORT6 TGG PORT7 GPIO0 GPIO4 TGR VDD RST
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PD7 VDD PD6 PD5 PD4 GND PD3 PD2 PD1 PD0 VDDI DSTRB DAFD DINIT DSLCIN DPE GNDI DSLC DERR DACK DBUSY GPIO7 VDD GPIO6 GPIO5 POE
GT-6816
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
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GT-6816
V. Pin Descriptions128 No. 44 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name MD4 MD5 SHS MD6 GNDC1 SHB MD7 MOE# MWE# H2/CLK PORT1_0 PORT1_1 H1/SP VDDC1 PORT1_2 PORT1_3 PLL_EN# VDDP X1 X2 GNDP GNDC2 GPIO1 GPIO2 GPIO3 GNDC3 RS PORT1_4 WAKEUP PORT1_5 TGB/LEDB PORT1_6 TGG/LEDG PORT71_ GPIO0 GPIO4 TGR/LEDR VDDC2 RESET GPIO5 GPIO6 VDDC3 GPIO7 DBUSY Reset State Type Driven Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state High High Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state I/O I/O O I/O P O I/O O O O I/O I/O O P I/O I/O I P I O P P I/O I/O I/O P O I/O I I/O O I/O O I/O I/O I/O O P I I/O I/O P I/O I 4mA 4mA 8mA 4mA 8mA 4mA 4mA 4mA 8mA 4mA 4mA 8mA 4mA 4mA Description External memory data bus bit 4 External memory data bus bit 5 CCD sample hold signal control signal External memory data bus bit 6 Core ground CCD sample hold reset control signal External memory data bus bit 7 External memory output enable External memory write enable CCD shift clock/CIS clock control signal uP port 1 bit 0 uP port 1 bit 1 CCD shift clock/CIS SP control signal Core power uP port 1 bit 2 uP port 1 bit 3 PLL enable control signal, with pull-down, not PLL power Crystal input Crystal output PLL ground Core ground GPIO bit 1 GPIO bit 2 GPIO bit 3 Core ground CCD reset signal uP port 1 bit 4 USB device remoter wakeup uP port 1 bit 5 CCD TG/CIS LED B channel control signal uP port 1 bit 6 CCD TG/CIS LED G channel control signal uP port 1 bit 7 GPIO bit 0 GPIO bit 4 CCD TG/CIS LED R channel control signal Core power Power on reset, high active GPIO bit 5 GPIO bit 6 Core power GPIO bit 7 Device parallel port (Busy) signal, with
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1
2
3 4 5 6
Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state
4mA 4mA 4mA 8mA 4mA 4mA 8mA 4mA 8mA 4mA 4mA 4mA 8mA
7 8 9 10
11 12 13 14 15
Tri-state Tri-state Tri-state
4mA 4mA 4mA
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GT-6816
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 DACK DERR DSLC GNDI1 GNDI2 DPE DSLCIN DINIT DAFD DSTRB VDDI1 PD0 PD1 PD2 PD3 GNDC4 PD4 PD5 PD6 VDDC4 PD7 HBUSY VDDI2 VDDI3 HACK HERR HSLC VDDI4 HPE HSLCIN HINIT GNDI3 HAFD HSTRB GNDI4 SDA SCL TEST GNDU DD+ VDDU I I I P P I O O O O P I/O I/O I/O I/O P I/O I/O I/O P I/O O P P O O O P O I I P I I P I/O I/O I P I/O I/O P Device parallel port (Ack) signal, with Device parallel port (Fault) signal Device parallel port (select) signal, with IO ground IO ground Device parallel port (Paper end) signal, Device parallel port (Select in) signal Device parallel port (Init) signal Device parallel port (Auto feed) signal Device parallel port (Strobe) signal IO power Parallel port data bus bit 0, with Parallel port data bus bit 1, with Parallel port data bus bit 2, with Parallel port data bus bit 3, with Core ground Parallel port data bus bit 4, with Parallel port data bus bit 5, with Parallel port data bus bit 6, with Core power, Parallel port data bus bit 7, with Host parallel port (Busy) signal I/O Power I/O Power Host parallel port (Ack) signal Host parallel port (Fault) signal, with Host parallel port (Select) signal I/O power Host parallel port (Paper end) signal Host parallel port (Select in) signal, with Host parallel port (Init) signal, with I/O ground Host parallel port (Auto feed) signal, Host parallel port (Strobe) signal, with I/O ground Serial EEPROM data line, PCB need Serial EEPROM clock line, PCB need For test only, with pull-down, not USB transceiver ground USB transceiver DUSB transceiver D+ USB transceiver power
16
Low Low Low Low Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state Low
24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA 24mA
17 18 19 20
21
Low Low Low Low
24mA 24mA 24mA 24mA
22 23
Tri-state Tri-state
4mA 4mA
24 25 26
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GT-6816
VI.Registers mapPPCR PPHAR PPLAR PPDR IVDHPR IVDLPR IVIR HADFR TGCR MOD6DR MOD6PR MOD16HR MOD16LR ADCLKRR ADCLKFR SHR6R SHF6R SHR8R SHF8R SHCR LEDRHR LEDRLR LEDFHR LEDFLR LEDCR TGMR RS1RR RS1FR RS2RR RS2FR SHRRR SHRFR SHSRR SHSFR H1RR H1FR H2RR H2FR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W `hff `hfe `hfd `hfc `hfb `hfa `hf9 `he4 `hff00 `hff01 `hff02 `hff03 `hff04 `hff05 `hff06 `hff07 `hff08 `hff09 `hff0a `hff0b `hff0c `hff0d `hff0e `hff0f `hff10 `hff11 `hff12 `hff13 `hff14 `hff15 `hff16 `hff17 `hff18 `hff19 `hff1a `hff1b `hff1c `hff1d `hff1e `hff1f Parallel port control register Parallel port high address register Parallel port low address register Parallel port data register Image valid data high pointer register Image valid data low pointer register Image valid indication register Host access device flag register TG Control Register Modulo 6 bit for dot clock Modulo 6 bit for pixel clock Modulo 16 bit high byte Modulo 16 bit low byte ADCLK rise register ADCLK fall register SH(TG) setup register(reference to 6bit counter) SH(TG) setup register(reference to 6bit counter) SH(TG) setup register(reference to 16bit counter) SH(TG) setup register(reference to 16bit counter) SH(TG) configuration register LED rise high register(reference to 16bit counter) LED rise low register(reference to 16bit counter) LED fall high register(reference to 16bit counter) LED fall low register(reference to 16bit counter) LED configuration register TG Mask register RS1 rise register RS1 fall register RS2 rise register RS2 fall register SHR rise register SHR fall register SHS rise register SHS fall register H1 rise register H1 fall register H2 rise register H2 fall register CLAMP 0 rise register CLAMP 0 fall register
CLAMP0RR R/W CLAMP0FR R/W
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GT-6816
Name CCLP0RR CCLP0FR CLAMP1RR CLAMP1FR CCLP1RR CCLP1FR CLAMP2RR CLAMP2FR CCLP2RR CCLP2FR CDSR0RR CDSR0FR CDSR1RR CDSR1FR CDSR2RR CDSR2FR CDSS0RR CDSS0FR CDSS1RR CDSS1FR CDSS2RR CDSS2FR CDSD0RR CDSD0FR CDSD1RR CDSD1FR CDSD2RR CDSD2FR MUXA0RR MUXA0FR MUXA1RR MUXA1FR MUXB0RR MUXB0FR MUXB1RR MUXB1FR OFFM0RR OFFM0FR OFFM1RR OFFM1FR PGAM0RR PGAM0FR PGAM1RR PGAM1FR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address `hff20 `hff21 `hff22 `hff23 `hff24 `hff25 `hff26 `hff27 `hff28 `hff29 `hff2a `hff2b `hff2c `hff2d `hff2e `hff2f `hff30 `hff31 `hff32 `hff33 `hff34 `hff35 `hff36 `hff37 `hff38 `hff39 `hff3a `hff3b `hff3c `hff3d `hff3e `hff3f `hff40 `hff41 `hff42 `hff43 `hff44 `hff45 `hff46 `hff47 `hff48 `hff49 `hff4a `hff4b
Description
CCLP 0 rise register CCLP 0 fall register CLAMP 1 rise register CLAMP 1 fall register CCLP 1 rise register CCLP 1 fall register CLAMP 2 rise register CLAMP 2 fall register CCLP 2 rise register CCLP 2 fall register CDSR channel 0 rise register CDSR channel 0 fall register CDSR channel 1 rise register CDSR channel 1 fall register CDSR channel 2 rise register CDSR channel 2 fall register CDSS channel 0 rise register CDSS channel 0 fall register CDSS channel 1 rise register CDSS channel 1 fall register CDSS channel 2 rise register CDSS channel 2 fall register CDSD channel 0 rise register CDSD channel 0 fall register CDSD channel 1 rise register CDSD channel 1 fall register CDSD channel 2 rise register CDSD channel 2 fall register MUXA_sel 0 rise register MUXA_sel 0 fall register MUXA_sel 1 rise register MUXA_sel 1 fall register MUXB_sel 0 rise register MUXB_sel 0 fall register MUXB_sel 1 rise register MUXB_sel 1 fall register OFFM_sel 0 rise register OFFM_sel 0 fall register OFFM_sel 1 rise register OFFM_sel 1 fall register PGAM_sel 0 rise register PGAM_sel 0 fall register PGAM_sel 1 rise register PGAM_sel 1 fall register
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GT-6816
Name GAINM0RR GAINM0FR GAINM1RR GAINM1FR DCR D1TBHR D1TBLR M1SAHR M1SALR M2SAHR M2SALR D2BCHR D2BCLR DMACR D2THR D2TLR D2SHR D2SLR RHR RLR CCR MBLHR MBLLR GPIOCR GPIODR WDTRR ASR ACR AC2R COFF0R CPGA0R COFF1R CPGA1R COFF2R CPGA2R SCR PPMCR PPHSR PPHDR PPDSR EDHSAR EDLSAR EDHBCR EDLBCR
R/W R/W R/W R/W R/W R/W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address `hff4c `hff4d `hff4e `hff4f `hff80 `hff81 `hff82 `hff83 `hff84 `hff85 `hff86 `hff88 `hff89 `hff8a `hff8b `hff8c `hff8d `hff8e `hff8f `hff90 `hff91 `hff92 `hff93 `hff94 `hff95 `hff96 `hff87 `hff97 `hff98 `hff99 `hff9a `hff9b `hff9c `hff9d `hff9e `hff9f `hffA0 `hffA1 `hffA2 `hffA3 `hffA5 `hffA6 `hffA7 `hffA8
Description
GAINM_sel 0 rise register GAINM_sel 0 fall register GAINM_sel 1 rise register GAINM_sel 1 fall register DMA Control Register DMA1 Transfer Byte Count High Byte Register DMA1 Transfer Byte Count Low Byte Register M1 Starting Address High Byte Register M1 Starting Address Low Byte Register M2 Starting Address High Byte Register M2 Starting Address Low Byte Register DMA2 byte count high register DMA2 byte count low register DMA configuration register DMA2 Transfer Count High Byte Register DMA2 Transfer Count Low Byte Register DMA2 Sync Count High Byte Register DMA2 Sync Count Low Byte Register Resolution High Byte Register Resolution Low Byte Register Compression Configuration Register Minimum Buffer length High Register Minimum Buffer length Low Register GPIO control register GPIO data register Watch Dog Timer Reset register AFE suspend register AFE configuration register AFE configuration 2 register CDS OFFSET for channel 0 CDS PGA for channel 0 CDS OFFSET for channel 1 CDS PGA for channel 1 CDS OFFSET for channel 2 CDS PGA for channel 2 Suspend Control Parallel port mode control register Parallel port Host Status register Parallel port Host Data register Parallel port Device Status register EPP/USB DMA3 high start address register EPP/USB DMA3 low start address register EPP DMA3 high byte count register EPP DMA3 low byte count register
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GT-6816
NAME GAINM0RR GAINM0FR GAINM1RR GAINM1FR DCR D1TBHR D1TBLR M1SAHR M1SALR M2SAHR M2SALR D2BCHR D2BCLR DMACR D2THR D2TLR D2SHR D2SLR RHR RLR CCR MBLHR MBLLR GPIOCR GPIODR WDTRR ASR ACR AC2R COFF0R CPGA0R COFF1R CPGA1R COFF2R CPGA2R SCR PPMCR PPHSR PPHDR PPDSR EDHSAR EDLSAR EDHBCR EDLBCR
R/W R/W R/W R/W R/W R/W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address `hff4c `hff4d `hff4e `hff4f `hff80 `hff81 `hff82 `hff83 `hff84 `hff85 `hff86 `hff88 `hff89 `hff8a `hff8b `hff8c `hff8d `hff8e `hff8f `hff90 `hff91 `hff92 `hff93 `hff94 `hff95 `hff96 `hff87 `hff97 `hff98 `hff99 `hff9a `hff9b `hff9c `hff9d `hff9e `hff9f `hffA0 `hffA1 `hffA2 `hffA3 `hffA5 `hffA6 `hffA7 `hffA8
Description GAINM_sel 0 rise register GAINM_sel 0 fall register GAINM_sel 1 rise register GAINM_sel 1 fall register DMA Control Register DMA1 Transfer Byte Count High Byte Register DMA1 Transfer Byte Count Low Byte Register M1 Starting Address High Byte Register M1 Starting Address Low Byte Register M2 Starting Address High Byte Register M2 Starting Address Low Byte Register DMA2 byte count high register DMA2 byte count low register DMA configuration register DMA2 Transfer Count High Byte Register DMA2 Transfer Count Low Byte Register DMA2 Sync Count High Byte Register DMA2 Sync Count Low Byte Register Resolution High Byte Register Resolution Low Byte Register Compression Configuration Register Minimum Buffer length High Register Minimum Buffer length Low Register GPIO control register GPIO data register Watch Dog Timer Reset register AFE suspend register AFE configuration register AFE configuration 2 register CDS OFFSET for channel 0 CDS PGA for channel 0 CDS OFFSET for channel 1 CDS PGA for channel 1 CDS OFFSET for channel 2 CDS PGA for channel 2 Suspend Control Parallel port mode control register Parallel port Host Status register Parallel port Host Data register Parallel port Device Status register EPP/USB DMA3 high start address register EPP/USB DMA3 low start address register EPP DMA3 high byte count register EPP DMA3 low byte count register
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GT-6816
NAME R/W Address Description
EDCR TISR UIS2R UIS1R TIER UIE2R UIE1R ISR DFR DBCARCR URLBCR URHBCR URLBCGIR URLBCGIR URT URC URVLB URVHB URILB URIHB URLLB URLHB UEIR DUSR DUTBCI8R DUTPS2R DUTPS1R DUTPC2R DUTPC1R DURPSR UECR UETSR UERSR UDAR UDCR UDSTR0 UDSTR1 UDSTR2 UDSTR3 UDSTR4 UDSTR5 UDSTR6 UDSTR7 UDCRR0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
`hffA9 `hffAA `hffAB `hffAC `hffAD `hffAE `hffAF `hffB0 `hffB1 `hffB2 `hffB3 `hffB4 `hffB5 `hffB6 `hffB8 `hffB9 `hffBA `hffBB `hffBC `hffBD `hffBE `hffBF `hffC0 `hffC1 `hffC2 `hffC3 `hffC4 `hffC5 `hffC6 `hffC7 `hffC8 `hffC9 `hffCA `hffCB `hffCC `hffD0 `hffD1 `hffD2 `hffD3 `hffD4 `hffD5 `hffD6 `hffD7 `hffD8
EPP/USB DMA3 control register Top Interrupt status Register USB Interrupt status 2 Register USB Interrupt status 1 Register Top Interrupt Enable Register USB Interrupt Enable 2 Register USB Interrupt Enable 1 Register Interrupt Select Register Device Flag register DMA3 byte count auto-reload control register USB Receive low byte count Register USB Receive high byte count Register USB Receive low byte count to generate IRQ USB Receive high byte count to generate IRQ USB Request Type USB Request Code USB Request Value Low Byte USB Request Value High Byte USB Request Index Low Byte USB Request Index High Byte USB Request Length Low Byte USB Request Length High Byte USB Endpoint index Register DMA3 USB Status Register DMA3 USB TX Byte Count for internal DMA3 USB TX Packet Size 2 Register DMA3 USB TX Packet Size 1 Register DMA3 USB TX Packet Count 2 (# of packet) DMA3 USB TX Packet Count 1 (# of packet) DMA3 USB Receive packet size Register USB Endpoint Control Register USB Endpoint Transmit Status Register USB Endpoint Receive Status Register USB Device Address Register USB Device Control Register USB Device Status Transmit Register 0 USB Device Status Transmit Register 1 USB Device Status Transmit Register 2 USB Device Status Transmit Register 3 USB Device Status Transmit Register 4 USB Device Status Transmit Register 5 USB Device Status Transmit Register 6 USB Device Status Transmit Register 7 USB Device Command Receive Register 0
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GT-6816
Name UDCRR1 UDCRR2 UDCRR3 UDCRR4 UDCRR5 UDCRR6 UDCRR7 R/W Address Description R R R R R R R
`hffD9 `hffDA `hffDB `hffDC `hffDD `hffDE `hffDF
USB Device Command Receive Register 1 USB Device Command Receive Register 2 USB Device Command Receive Register 3 USB Device Command Receive Register 4 USB Device Command Receive Register 5 USB Device Command Receive Register 6 USB Device Command Receive Register 7
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Registers Definitions Timing Generator Setup Register
CPU Read/Write
Address: FF00H
Bit 7:4 Reset 4'b0 Description Reserved
Select LED control signal output to PEPP_AD0~PEPP_AD2 for the sake of driving issue. When this bit is set, the mapping of pins are changed to:
PTGR PTGG PTGB = TG_R, = TG_G, = TG_B,
3
1'b0
PEPP_AD0 = LED_R, PEPP_AD1 = LED_G, PEPP_AD2 = LED_B;
Note: TG_R, TG_G, TG_B are TG signal for R, G, B channel. LED_R, LED_G, LED_B are LED signal for R, G, B channel. These signals are programmable by register definitions. TG rise event enable : 0 = disable TG rise event. 1 = enable TG rise event. TG event will occur when TG signal changes state from `0' to `1' Sensor type : 0 = CIS 1 = CCD As select in CIS mode, PH1 will output TG signal and controlled by H1_pol and H1_en. Global Timing Generator enable control.
2
1'b1
1
1'b0
0
1'b0
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GT-6816
Referenced period for 6-bits dot clock counter: CPU Read/Write
Address: FF01H Bit 7:6 5:0 Reset Description 2'b0 Reserved Defines the referenced period (N+1) cycles of the 6 bits dot clock counter. 6'b0 The 6-bits dot clock counter is referenced by master clock (48MHz). Dot clock is defined by this N+1 cycles referenced to 6-bits dot clock counter.
Referenced period for 6-bits pixel clock counter: CPU Read/Write
Address: FF02H Bit 7:6 Reset Description 2'b0 Reserved Defines the referenced period (N+1) cycles of the 6 bits pixel clock counter. The 6-bits pixel clock counter is referenced by master clock (48MHz). Pixel clock is defined by this N+1 cycles referenced to 6-bits 6'b0 pixel clock counter. The programmable timing control signal for sensor and AFE are referenced to pixel clock.
5:0
Referenced period high byte for 16-bits counter of timing generator: CPU Read/Write
Address: FF03H Bit 7:0 Reset Description 8'b0 Period for 16-bits counter high byte
Referenced period low byte for 16-bits counter of timing generator:
Address: FF04H Bit Reset Description Period for 16-bits counter low byte. These two registers define the period (N+1) cycles of 16-bits counter 8'b0 referenced to pixel clock. All programmable timing control signals are referenced to this 16-bits counter.
7:0
AFE ADCLK rising phase control CPU Read/Write
Address: FF05H Bit 7:6 5:0 Reset Description 2'b0 6'b0 Reserved Define ADCLK rising phase referenced to 6-bits dot clock counter
AFE ADCLK falling phase control 12
GT-6816
CPU Read/Write
Address: FF06H Bit 7:6 5:0 Reset Description 2'b0 Reserved 6'b0 Define ADCLK falling phase referenced to 6-bits dot clock counter
Sensor TG control signal rising phase referenced to pixel counter CPU Read/Write
Address: FF07H Bit 7:6 5:0 Reset Description 2'b0 Reserved 6'b0 Define TG rising phase reference to 6-bits pixel counter
Sensor TG control signal falling phase referenced to pixel counter
Address: FF08H Bit 7:6 5:0 Reset Description 2'b0 Reserved 6'b0 Define TG falling phase referenced to 6-bits pixel counter
Sensor TG signal rising phase referenced to 16-bits counter: CPU Read/Write
Address: FF09H Bit 7:0 Reset Description 8'b0 Define TG rising phase referenced to 16-bit counter
Sensor TG signal falling phase referenced to 16-bits counter: CPU Read/Write
Address: FF0AH Bit 7:0 Reset Description 8'b0 Define TG falling phase referenced to 16-bit counter
Note : The conditions for rising and falling only available during first 256 cycles of 16-bits counter. For cycle exceeds 256 of 16-bits counter, TG output `0' state.
Sensor TG control signal configuration
CPU Read/Write
Address: FF0BH
Bit 7:6
Reset Description 8'b0 Reserved
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GT-6816
5 1'b0 TG_B polarity 4 1'b0 TG_B enable 3 1'b0 TG_G polarity 2 1'b0 TG_G enable 1 1'b0 TG_R polarity 0 1'b0 TG_R enable Note : all these bits are synchronous with TG rising edge. Polarity = 0 : normal output as programming output Polarity = 1 : invert output from programming output Enable = 0 : disable control signal output Enable = 1 : enable programming output.
Sensor LED control signal rising phase high byte CPU Read/Write
Address: FF0CH Bit 7:4 3:0 Reset Description 4'b0 Reserved 4'b0 Define rising phase bit11~bit8
Sensor LED control signal rising phase low byte CPU Read/Write Address: FF0DH
Bit 7:0
Reset Description 8'b0 Define rising phase bit7~bit0
Sensor LED control signal falling phase high byte CPU Read/Write Address: FF0EH
Bit 7:4 3:0
Reset Description 4'b0 4'b0 Reserved Define falling phase bit11~bit8
Sensor LED control signal falling phase low byte CPU Read/Write Address: FF0FH
Bit 7:0
Reset Description 8'b0 Define falling phase bit7~bit0
Note: The programming rising and falling phase are referenced to 16-bit counter with 12 MSB. Bit 7:6 5 Reset Description 8'b0 Reserved 1'b0 LED_B polarity
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GT-6816
4 1'b0 LED_B enable 3 1'b0 LED_G polarity 2 1'b0 LED_G enable 1 1'b0 LED_R polarity 0 1'b0 LED_R enable Note : all these bits are synchronous with TG rising edge. Polarity = 0 : normal output as programming output Polarity = 1 : invert output from programming output Enable = 0 : disable control signal output Enable = 1 : enable programming output.
Sensor TG mask period control register CPU Read/Write Address: FF11H
Bit
7:0
Reset Description Define TG mask period. This mask signal will go active when initial the 16-bits counter and clear after N cycles of pixel clock. During this period 8'b0 internal sensor control signal RS1, RS2, H1, and H2 will enter idle state, i.e. , output `0' when this masking function is enable.
Sensor RS1 control signal rising phase CPU Read/Write Address: FF12H
Bit 7
Reset Description RS1 polarity 1'b0 0 = normal operation. 1 = invert RS1 output RS1 enable 1'b0 0 = disable RS1 output 1 = enable RS1 output 6'b0 Define rising phase referenced to 6-bits pixel clock counter
6 5:0
Sensor RS1 control signal falling phase CPU Read/Write Address: FF13H
Bit 7
Reset Description 1'b0 Reserved
15
GT-6816
6 5:0 RS1 masking function enable 1'b0 0 = disable masking function 1 = enable masking function 6'b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor RS2 control signal rising phase CPU Read/Write Address: FF14H
Bit 7
Reset Description RS2 polarity 1'b0 0 = normal operation. 1 = invert RS2 output RS2 enable 1'b0 0 = disable RS2 output 1 = enable RS2 output 6'b0 Define rising phase referenced to 6-bits pixel clock counter
6 5:0
Sensor RS2 control signal falling phase CPU Read/Write Address: FF15H
Bit 7 6 5:0
Reset Description 1'b0 Reserved RS2 masking function enable 1'b0 0 = disable masking function 1 = enable masking function 6'b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor SHR control signal rising phase CPU Read/Write Address: FF16H
Bit 7
Reset Description SHR polarity 1'b0 0 = normal operation 1 = invert SHR output 1'b0 6'b0 SHR enable 0 = disable SHR ouptut 1 = enable SHR output Define rising phase referenced to 6-bits pixel clock counter
6 5:0
Sensor SHR control signal falling phase CPU Read/Write Address: FF17H
16
GT-6816
Bit 7:6 5:0 Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor SHS control signal rising phase CPU Read/Write Address: FF18H
Bit 7
Reset Description SHS polarity 1'b0 0 = normal operation 1 = invert SHS output 1'b0 6'b0 SHS enable 0 = disable SHS ouptut 1 = enable SHS output Define rising phase referenced to 6-bits pixel clock counter
6 5:0
Sensor SHS control signal falling phase CPU Read/Write Address: FF19H
Bit 7:6 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor H1 control signal rising phase CPU Read/Write Address: FF1AH
Bit 7
Reset Description H1 polarity 1'b0 0 = normal operation. 1 = invert H1 output H1 enable 1'b0 0 = disable H1 output 1 = enable H1 output 6'b0 Define rising phase referenced to 6-bits pixel clock counter
6 5:0
Sensor H1 control signal falling phase CPU Read/Write Address: FF1BH
Bit 7 6
Reset Description 1'b0 H1 half enable H1 masking function enable 1'b0 0 = disable masking function 1 = enable masking function
17
GT-6816
5:0 6'b0 Define falling phase referenced to 6-bits pixel clock counter
Sensor H2 control signal rising phase CPU Read/Write Address: FF1CH
Bit 7
Reset Description 1'b0 H2 polarity 0 = normal operation. 1 = invert H2 output 1'b0 H2 enable 0 = disable H2 output 1 = enable H2 output 6'b0 Define rising phase referenced to 6-bits pixel clock counter
6
5:0
Sensor H2 control signal falling phase CPU Read/Write Address: FF1DH
Bit 7 6
5:0
Reset Description 1'b0 H2 half enable 1'b0 H2 masking function enable 0 = disable masking function 1 = enable masking function 6'b0 Define falling phase referenced to 6-bits pixel clock counter
AFE CLAMP0 control signal rising phase CPU Read/Write Address: FF1EH
Bit 7:0
Reset Description 8'b0 Define rising phase referenced to 16-bits counter
AFE CLAMP0 control signal falling phase CPU Read/Write Address: FF1FH
Bit 7:0
Reset Description 8'b0 Define falling phase referenced to 16-bits counter
Note: These two registers define the rising and falling phase of CLAMP0 control signal, and only available on the first 256 cycles of 16-bits counter. CLAMP0 output `0' when 16-bits counter exceeds 256 cycle.
AFE CCLP0 control signal rising phase CPU Read/Write Address: FF20H
18
GT-6816
Bit 7 Reset Description CLAMP0 enable 1'b0 0 = CLAMP0 output disable 1 = CLAMP0 output enable 1'b0 6'b0 CCLP0 enable 0 = CCLP0 output disable 1 = CCLP0 output enable Define rising phase referenced to 6-bits pixel clock counter
6 5:0
AFE CCLP0 control signal falling phase CPU Read/Write Address: FF21H
Bit 7:6 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel counter
AFE CLAMP1 control signal rising phase CPU Read/Write Address: FF22H
Bit 7:0
Reset Description 8'b0 Define rising phase referenced to 16-bits counter
AFE CLAMP1 control signal falling phase CPU Read/Write Address: FF23H
Bit Reset Description 7:0 8'b0 Define falling phase referenced to 16-bits counter Note: These two registers define the rising and falling phase of CLAMP1 control signal, and only available on the first 256 cycles of 16-bits counter. CLAMP1 output `0' when 16-bits counter exceeds 256 cycle.
AFE CCLP1 control signal rising phase CPU Read/Write Address: FF24H
Bit
6
Reset Description CLAMP1 enable 1'b0 0 = CLAMP1 output disable 1 = CLAMP1 output enable CCLP1 enable 1'b0 0 = CCLP1 output disable 1 = CCLP1 output enable
19
GT-6816
5:0 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE CCLP1 control signal falling phase CPU Read/Write Address: FF25H
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CLAMP2 control signal rising phase CPU Read/Write Address: FF26H
Bit 7:0
Reset Description 8'b0 Define rising phase referenced to 16-bits counter
AFE CLAMP2 control signal falling phase CPU Read/Write Address: FF27H
Bit
Reset Description
7:0 8'b0 Define falling phase referenced to 16-bits counter Note: These two registers define the rising and falling phase of CLAMP2 control signal, and only available on the first 256 cycles of 16-bits counter. CLAMP2 output `0' when 16-bits counter exceeds 256 cycle.
AFE CCLP2 control signal rising phase CPU Read/Write Address: FF28H
Bit 7
Reset Description 1'b0 CLAMP2 enable 0 = CLAMP2 output disable 1 = CLAMP2 output enable CCLP2 enable 0 = CCLP2 output disable 1 = CCLP2 output enable Define rising phase referenced to 6-bits pixel counter
6 5:0
1'b0 6'b0
AFE CCLP2 control signal falling phase CPU Read/Write
20
GT-6816
AFE CDSR0 control signal rising phase CPU Read/Write Address: FF2AH
Bit 7 6 5:0
Reset Description 1'b0 1'b0 6'b0 Reserved CDSR0 enable 0 = CDSR0 output disable 1 = CDSR0 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSR0 control signal falling phase CPU Read/Write Address: FF2BH
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CDSR1 control signal rising phase CPU Read/Write Address: FF2CH
Bit 7 6 5:0
Reset Description 1'b0 1'b0 6'b0 Reserved CDSR1 enable 0 = CDSR1 output disable 1 = CDSR1 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSR1 control signal falling phase CPU Read/Write Address: FF2DH
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CDSR2 control signal rising phase CPU Read/Write Address: FF2EH
Bit 7
Reset Description 1'b0 Reserved
21
GT-6816
6 5:0 1'b0 6'b0 CDSR2 enable 0 = CDSR2 output disable 1 = CDSR2 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSR2 control signal falling phase CPU Read/Write Address: FF2FH
Bit 7:6 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel counter
AFE CDSS0 control signal rising phase CPU Read/Write Address: FF30H
Bit 7 6 5:0
Reset Description 1'b0 Reserved CDSS0 enable 1'b0 0 = CDSS0 output disable 1 = CDSS0 output enable 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE CDSS0 control signal falling phase CPU Read/Write Address: FF31H
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CDSS1 control signal rising phase CPU Read/Write Address: FF32H
Bit 7 6 5:0
Reset Description 1'b0 Reserved CDSS1 enable 1'b0 0 = CDSS1 output disable 1 = CDSS1 output enable 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE CDSS1 control signal falling phase CPU Read/Write
Address: FF33H 22
GT-6816
Bit 7:6 5:0 Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CDSS2 control signal rising phase CPU Read/Write Address: FF34H
Bit 7 6 5:0
Reset Description 1'b0 Reserved CDSS2 enable 1'b0 0 = CDSS2 output disable 1 = CDSS2 output enable 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE CDSS2 control signal falling phase CPU Read/Write Address: FF35H
Bit 7:6 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel counter
AFE CDSD0 control signal rising phase
CPU Read/Write
Address: FF36H
Bit 7 6 5:0
Reset Description 1'b0 1'b0 6'b0 Reserved CDSD0 enable 0 = CDSD0 output disable 1 = CDSD0 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSD0 control signal falling phase
CPU Read/Write Address: FF37H
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE CDSD1 control signal rising phase CPU Read/Write 23
GT-6816
Address: FF38H
Bit 7 6 5:0
Reset Description 1'b0 1'b0 6'b0 Reserved CDSD1 enable 0 = CDSD1 output disable 1 = CDSD1 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSD1 control signal falling phase CPU Read/Write Address: FF39H
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define rising phase referenced to 6-bits pixel counter
AFE CDSD2 control signal rising phase CPU Read/Write Address: FF3AH
Bit 7 6 5:0
Reset Description 1'b0 Reserved 1'b0 6'b0 CDSD2 enable 0 = CDSD2 output disable 1 = CDSD2 output enable Define rising phase referenced to 6-bits pixel counter
AFE CDSD2 control signal falling phase CPU Read/Write Address: FF3BH
Bit 7:6 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE MUXA0 control signal rising phase CPU Read/Write Address: FF3CH
Bit 7 6
Reset Description Polarity 1'b0 0 = normal operation 1 = invert MUXA0 output signal 1'b0 Enable 0 = disable MUXA0 output 1 = enable MUXA0 output
24
GT-6816
5:0 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXA0 control signal falling phase CPU Read/Write Address: FF3DH
Bit 7:0 5:0
Reset Description 2'b0 Reserved 6'b0 Define rising phase referenced to 6-bits pixel counter
AFE MUXA1 control signal rising phase CPU Read/Write Address: FF3EH
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert MUXA1 output signal 1'b0 6'b0 Enable 0 = disable MUXA1 output 1 = enable MUXA1 output Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE MUXA1 control signal falling phase CPU Read/Write Address: FF3FH
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE MUXB0 control signal rising phase CPU Read/Write Address: FF40H
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert MUXB0 output signal 1'b0 6'b0 Enable 0 = disable MUXB0 output 1 = enable MUXB0 output Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE MUXB0 control signal falling phase CPU Read/Write Address: FF41H
25
GT-6816
Bit 7:0 5:0 Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE MUXB1 control signal rising phase CPU Read/Write Address: FF42H
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert MUXB1 output signal Enable 1'b0 0 = disable MUXB1 output 1 = enable MUXB1 output 6'b0 Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE MUXB1 control signal falling phase CPU Read/Write Address: FF43H
Bit 7:0 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel counter
AFE OFFSET Select 0 control signal rising phase CPU Read/Write Address: FF44H
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert OFFSET Select 0 control signal output Enable 1'b0 0 = disable OFFSET Select 0 control signal output 1 = enable OFFSET Select 0 control signal output 6'b0 Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE OFFSET Select 0 control signal falling phase CPU Read/Write Address: FF45H
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE OFFSET Select 1 control signal rising 26
GT-6816
CPU Read/Write Address: FF46H
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert OFFSET Select 1 control signal output 1'b0 6'b0 Enable 0 = disable OFFSET Select 1 control signal output 1 = enable OFFSET Select 1 control signal output Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE OFFSET Select 1 control signal falling CPU Read/Write Address: FF47H
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE PGA Select 0 control signal rising phase CPU Read/Write Address: FF48H
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert PGA Select 0 control signal output 1'b0 6'b0 Enable 0 = disable PGA Select 0 control signal output 1 = enable PGA Select 0 control signal output Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE PGA Select 0 control signal falling phase CPU Read/Write Address: FF49H
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE PGA Select 1 control signal rising phase CPU Read/Write Address: FF4AH
Bit
Reset Description
27
GT-6816
7 Polarity 1'b0 0 = normal operation 1 = invert PGA Select 1 control signal output 1'b0 6'b0 Enable 0 = disable PGA Select 1 control signal output 1 = enable PGA Select 1 control signal output Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE PGA Select 1 control signal falling phase CPU Read/Write Address: FF4BH
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE GAIN Select 0 control signal rising phase CPU Read/Write Address: FF4CH
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert GAIN Select 0 control signal output Enable 1'b0 0 = disable GAIN Select 0 control signal output 1 = enable GAIN Select 0 control signal output 6'b0 Define rising phase referenced to 6-bits pixel counter
6 5:0
AFE GAIN Select 0 control signal falling phase CPU Read/Write Address: FF4DH
Bit 7:0 5:0
Reset Description 2'b0 6'b0 Reserved Define falling phase referenced to 6-bits pixel counter
AFE GAIN Select 1 control signal rising phase CPU Read/Write Address: FF4EH
Bit 7
Reset Description Polarity 1'b0 0 = normal operation 1 = invert GAIN Select 1 control signal output
28
GT-6816
6 5:0 1'b0 6'b0 Enable 0 = disable GAIN Select 1 control signal output 1 = enable GAIN Select 1 control signal output Define rising phase referenced to 6-bits pixel counter
AFE GAIN Select 1 control signal falling phase CPU Read/Write Address: FF4FH
Bit 7:0 5:0
Reset Description 2'b0 Reserved 6'b0 Define falling phase referenced to 6-bits pixel counter
DMA control register CPU Read/Write Address: FF80H
Bit
7
Reset Description Last scan line: 0 = not last scan line 1 = current scan is last line 1'b0 When do last line scan, CPU must set this bit to inform the controller the next DMA2 transfer is the last line scan. Clear this bit automatically when DMA2 is done. Disable DMA2 write to M2 0 = DMA2 write data to M2 is enable 1 = skip current DMA2 writing data to M2 1'b0 When this bit is set, the current DMA2 writing data to M2 will be disable. DMA2 transfer count will not increment during this bit set high. DMA2 event will be triggered. 3'b0 Reserved SROM download 0 = normal operation 1 = re-download code from external EEPROM 1'b0 When this command is requested, CPU will enter reset state and re-download the program code stored in external EEPROM. The starting address must be defined before set this command. When download is completed, CPU is running with the download program code.
6
5:4
3
29
GT-6816
DMA3 enable read image DMA3 is defined as the transfer between M2 and PC interface (ECP, EPP, or USB). When this bit is set to `1', the incoming DMA3 transfer indicates the transfer of image data to PC interface. The image valid data byte count will decrement by one automatically when DMA3 is a read transfer and this bit is set to one. If this bit is cleared to `0', the request for read/write M2 by PC interface is just the memory access. If the last line scanning is present, this bit will also be cleared automatically when DMA2 is completed. DMA2 enable 0 = DMA2 is disable 1 = DMA2 is enable DMA2 is defined as the transfer from sensor input via AFE to M2. When each line scan is complete, DMA2 event occurs and DMA2 enable bit is cleared automatically. The address is started from the current M2 starting address and incremented automatically. CPU can poll this bit to determine the line scan is end or not. If overrun occurs, i.e., the image buffer is not enough to store the incoming image data, this bit will be cleared and disable the DMA2 transfer. In this condition, interrupt will be generated. DMA1 enable DMA1 is defined as the transfer from M2 to M1. The purpose of DMA1 is to download the updated program code to M1. The updated program code must be stored in M2 before DMA1 is active. When this bit is set to `1', DMA1 is active. CPU will be halted and transfer data from M2 to M1. This bit will be clear automatically when DMA1 transfer is done.
2
1'b0
1
1'b0
0
1'b0
DMA1 transfer bytes Count high byte register CPU Read/Write Address: FF81H
Bit 7:0
Reset Description 8'b0 DMA1 transfer byte count high byte
DMA1 transfer bytes count low byte register CPU Read/Write Address: FF82H
Bit
Reset Description
30
GT-6816
7:0 8'b0 DMA1 transfer byte count low byte Note: DMA1 transfer bytes count indicates the total bytes that will be transferred from M2 to M1. Before DMA1 is active, set these two registers first.
DMA1 M1 starting address high byte register CPU Read/Write Address: FF83H
Bit 7:0
Reset Description 8'b0 M1 starting address high byte
DMA1 M1 starting address low byte register CPU Read/Write Address: FF84H
Bit
Reset Description
7:0 8'b0 M1 starting address low byte Note: DMA1 starting address indicates the initial address when DMA1 is on going. Address is automatically increment by one when one byte transfer is done.
DMA M2 starting address high byte register CPU Read/Write Address: FF85H
Bit 7:0
Reset Description 8'b0 M2 starting address high byte
DMA M2 starting address high byte register CPU Read/Write Address: FF86H
Bit 7:0
Reset Description 8'b0 M2 starting address low byte
Note: These two registers define the M2 starting address when DMA1 or DMA2 transfer are enable. Note that these two registers are changed on the fly during DMA1 and DMA2. Be careful to set the real initial address before DMA1 or DMA2 is enable.
DMA2 valid byte count high register CPU Read/Write
Bit 7:0
Reset Description 8'b0 DMA2 valid byte count high byte
31
GT-6816
DMA2 valid byte count low register CPU Read/Write Address: FF89H
Bit 7:0
Reset Description 8'b0 DMA2 valid byte count low byte
Note: These two registers record the valid byte count left in M2. This counter will be increment when DMA2 transfer occurs, and decrement when DMA3 transfer has been issued. Before starting scan first line, CPU has to write `0' to clear contents of these two registers. In normal scanning image process, CPU writes to these two registers are not recommended.
DMA configuration register CPU Read/Write Address: FF8AH
Bit
Reset Description AFE data valid phase This phase defines the AFE data valid phase referenced to 6-bit dot clock 6'b0 counter of Timing Generator. This phase can be modified to fit the optimized quality of AFE output data . Reset DMA2 FIFO 0 = normal operation 1'b0 1 = reset DMA2 FIFO. Always return `0' when CPU read this bit. Select external memory The external memory is now supported to 64K bytes SRAM. ** Entering suspend mode: 1'b0 1. Writing expected output data to M2. (CPU cycle) 2. Suspend M2 3. Pin PMDx will output the previous write data to avoid floating output.
7:2
1
0
DMA2 transfer count high byte register CPU Read/Write Address: FF8BH
Bit 7:0
Reset Description 8'b0 DMA2 transfer count high byte
DMA2 transfer count low byte register 32
GT-6816
CPU Read/Write Address: FF8CH
Bit
Reset Description DMA2 transfer count low byte
7:0 8'b0 Note:
When DMA2 begins to transfer, these two registers defines the pixel count per line, i.e., when transfer reaches the count defined in these two register, transfer will stop and interrupt will occurs. Also DMA2 enable bit will be cleared. To enable the next line scan, set DMA2 enable again.
DMA2 bypass count high byte register CPU Read/Write Address: FF8DH
Bit 7:0
Reset Description 8'b0 DMA2 bypass count high byte
DMA2 bypass count low byte register CPU Read/Write Address: FF8EH
Bit
Reset Description DMA2 bypass count low byte
7:0 8'b0 Note:
These two registers define the dummy pixel count when DMA2 is enable. Note that DMA2 will be synchronized with TG signal (falling edge) and bypass the dummy pixels count defined here, the following data will be really image data and writes to M2.
DPI setting high byte register CPU Read/Write
Address: FF8FH Bit 7:2 1:0 Reset Description 8'b0 2'h2 Reserved Dpi setting high byte
DPI setting low byte register CPU Read/Write
Address: FF90H
33
GT-6816
Bit Reset Description 7:0 8'h58 Dpi setting low byte Note: DPI = (optical sensor dpi) x (dpi setting)/600 For example, if optical sensor is 600 dpi, to get 300 dpi output we set: DPI = (600) x (300/600) = 300 dpi Dpi setting must be set to 300 (12c:heximal).
Data type configuration register CPU Read/Write
Address: FF91H Bit 7 6 5 4 Reset Description 1'b0 1'b0 1'b0 1'b0 Reserved Inverse AFE data When this bit is set the AFE output data will be inverted. CCR[5] Scan mode 0 = line mode 1 = pixel mode
CCR[5]
3:0
4'b01 CCR[3:0] CCR[1:0] CCR[3:2] 2'bxx 2'bxx 2'bx1 2'b10 2'b00 2'b10 2'b00 2'b01 2'bx0 2'bx1 2'bxx 2'bxx 2'bxx 2'bxx 2'bxx 2'bxx 2'bxx Description 7 bits compression 6 bits compression 8 bits optimize 10 bits non-optimize 12 bits non-optimize 10 bits optimize 12 bits optimize 14 bits non-optimize 16 bits optimize 1'b1 1'b1 1'b0 1'b0 1'b0 1'b0 1'b0 1'b0
TSTR.0
1'bx 1'bx 1'b0 1'b0 1'b0 1'b1 1'b1 1'b1
1'b1 1'b0 2'b11 TSTR.0 = test register bit 0
DMA3 minimum buffer length high byte register
CPU Read/Write
Address: FF92H
Bit
Reset Description
34
GT-6816
7:0 8'h0 DMA3 minimum buffer length high byte
DMA3 minimum buffer length low byte register CPU Read/Write Address: FF93H
Bit
Reset Description
7:0 8'h40 DMA3 minimum buffer length low byte Note: These registers define the minimum buffer length when DMA3 transfer is enabled. If the size of images stored in image buffer is less than defined values, controller will decode not ready signal to USB or EPP, or ECP controller. In the last line scan process, when DMA2 is completed, the not ready signal will be cleared no matter image buffer bytes count are larger or less than these registers.
General-purpose I/O pin control register CPU Read/Write Address: FF94H
Bit 7:0
Reset Description 8'h00 GPIO_en[7:0] 0 = set PGPIOx to input mode 1 = set PGPIOx to output mode
GPIO Data Register CPU Read/Write Address: FF95H
Bit 7:0
Reset Description 8'h00 GPIO_data[7:0] In input mode, read will return corresponding pin status. While in output mode, writing data to this register will simultaneously output to corresponding pin.
Watch Dog Timer Reset port CPU Write Address: FF96H
Bit 7:0
Reset Description 8'hxx Writing values to this register with 68h, then 01h will cause resetting of watch-dog-timer. If CPU exceeds 500ms not reset this register, hardware reset will occurs.
AFE suspend register CPU Write
35
GT-6816
Address: FF87H
Bit 7 6 5 4 3 2 1 0 Reset Description 1'b0 Status of DEV_WAKEUP (Read) 1'b0 Reserved 1'b1 BIAS_PD2 1'b1 CDS_PD2 1'b1 CDS_PD1 1'b1 CDS_PD0 1'b1 PGA_PD 1'b1 ADC_PD
AFE configuration register CPU Write
Address: FF97H Bit 7:4 3 2 1:0 Reset 2'b00 1'b0 1'b0 2'b0 Description Vref_sel2[3:0] Reserved AFE CDS_CTL signal AFE Switch select
AFE configuration 2 register CPU Write
Address: FF98H Bit 7:4 3:0 Reset Description 4'b0 Vref_sel1[3:0] 4'b0 Vref_sel0[3:0]
AFE CDS Offset 0 register CPU Write
Address: FF99H Bit 7:6 5:0 Reset Description 2'b00 Reserved 6'b0 AFE CDS OFFSET for channel 0
AFE CDS PGA 0 register CPU Write
Address: FF9AH Bit Reset Description
7:6 5
2'b00 Reserved 1'b0 AFE CDS gain for channel 0
36
GT-6816
4:0 6'b0 AFE CDS PGA for channel 0
AFE CDS Offset 1 register CPU Write
Address: FF9BH Bit 7:6 5:0 Reset Description 2'b00 Reserved 6'b0 AFE CDS OFFSET for channel 1
AFE CDS PGA 1 register CPU Write
Address: FF9CH Bit 7:6 5 4:0 Reset Description 2'b00 Reserved 1'b0 6'b0 AFE CDS gain for channel 1 AFE CDS PGA for channel 1
AFE CDS Offset 2 register CPU Write
Address: FF9DH Bit 7:6 5:0 Reset Description 2'b00 Reserved 6'b0 AFE CDS OFFSET for channel 2
AFE CDS PGA 2 register CPU Write
Address: FF9EH Bit 7:6 5 4:0 Reset Description 2'b00 Reserved 1'b0 6'b0 AFE CDS gain for channel 2 AFE CDS PGA for channel 2
Suspend control register CPU Read/Write
Address: FF9FH Bit 7 6 Reset Description 1'b0 1'b0 cpu_suspend Suspend X1
5
1'b0
Suspend 6803
37
GT-6816
4 3 2 1 0 1'b0 1'b0 1'b0 1'b0 1'b0 Select low speed Disable PLL reference clock input Suspend PLL Suspend 6802 Suspend M2
TEST register CPU Read/Write
Address: FFFFH Bit 7:1 0 Reset Description 1'b0 Always write `0' to these bits 1'b0 AFE select optimize mode
Parallel Port Control Register 38
GT-6816
EPP Host Read/Write (EPP access only)
Address: FFH
Bit 7-6 Reset Description 2'b00 Load program time-out control. Time-out for loading program is controlled by the most significant two bits of this 29-bit counter. Bit7 Bit6 0 0 1 1 5-4 3 0 1 0 1 : Don't care bit 28/27 : Don't care bit 28, care bit 27 : Don't care bit 27, care bit 28 : Care bit 28/27
2'b00 Reserved 0 Disable time-out counter to self-clear Parallel Port Interface Pass control. 0:enable counter ; 1: disable counter
2
0
Data Access Request: This bit is set when S/W starts to access data, and will be cleared automatically after finishing the data access.
1
0
Data Access Acknowledge: This bit is set whenever the data access request from bit 2 is finished. This bit will be cleared automatically when Data Access Request (bit 2) is set by software.
0
1
Read/Write: This bit indicates the direction of EPP host access program RAM. 1: Write 0: Read (for M1_enable)
Parallel Port High Address Register EPP Host Read/Write (EPP access only)
Address: FEH
Bit 7-0 Reset Description Address bit 15-8 of program RAM. This register defines the high address of EPP host access program RAM. Parallel Port Low Address Register EPP Host Read/Write (EPP access only)
Address: FDH
Bit 7-0 Reset Description Address bit 7-0 of program RAM. This register defines the low address of EPP host access program RAM. Parallel Port Data Register EPP Host Read/Write (EPP access only)
Address: FCH Bit Reset Description 7-0 - 8-bit data for EPP host access GT6816.
Image Data Valid High Pointer Register 39
GT-6816
EPP Host Read/Write (EPP access only)
Address: FBH Bit Reset Description 7 - 0 8'h00 This byte reflects the high address bit 15-8 of valid image data in buffer.
Image Data Valid High Pointer Register EPP Host Read/Write (EPP access only)
Address: FAH Bit 7-0 Reset Description 8'h00 This byte reflects the low address bit 7-0 of valid image data in buffer.
Image Valid Indication Register EPP Host Read/Write (EPP access only)
Address: F9H Bit Reset Description 7-1 - Reserved. 0 0 Indication of image data. 0/1: invalid/valid
Host Access Device Flag Register
EPP Host Read/Write (EPP access only)
Address: E4H Bit Reset Description 7-0 0 When read, the data reflects Device Flag Register which has CPU address FFB1h. When write, the data is used to handshake with device, default value is 8'h00. Note: EPP host access this port must issue ASTROBE# with address E4h first. During DMA3 transfer, EPP host must issue another ASTROBE# with new address.
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Parallel Port Mode Control Register CPU Read/Write Address: FFA0H
Bit 7 6 5 4 3
Reset Description This bit is used to select HOST or PRINTER bus to be read from 0 address FFA1h and address FFA3h. (RD_PRINTER). 0/1 : HOST / 0 GT6816 will be forced to scanner mode if this bit is high "1". This is read only bit to reflect scanner mode or pass-through mode. 0/1 : pass-through mode / scanner mode Clear scanner mode and changes to pass-through mode. 1/0: clear / no 0 action 0 Printer chain control selection. After loading the program, this bit must be set, in order to control the chain printer by bit 4. Parallel Port Mode selection. Bit2 Bit1 Bit0 1 0 0 Controlled by S/W 0 0 0 EPP mode , controlled by H/W automatically 0 0 1 ECP mode, controlled by H/W automatically
2-0
000
Notes: 1. There are three methods to enter scanner mode: (a) After protect / release sequence (b) After scanner mode data sequence (c) After setting bit 6 of address FFA0h 2. Only one way to return pass-through mode: Set bit 4 of address FFA0h Parallel Port Host Status Register CPU Read/Write Address: FFA1H
Bit 7 6 5 4 3 2 1 0
Reset Description IN / OUT selection of bit 3 of data bus of host parallel port. When output is 1 selected, bit 7 of FFA3h must be set to high. 0 / 1 : Output / Input IN / OUT selection of bit 2 of data bus of host parallel port. When output is 1 selected, bit 7 of FFA3h must be set to high. 0 / 1 : Output / Input 1 1 IN / OUT selection of bit 1 of data bus of host parallel port. When output is selected, bit 7 of FFA3h must be set to high. 0 / 1 : Output / Input IN / OUT selection of bit 0 of data bus of host parallel port. When output is selected, bit 7 of FFA3h must be set to high. 0 / 1 : Output / Input Status bit for HostClk (ECP) / nWrite (EPP) / nStrobe (SPP) Status bit for HostAck (ECP) / nDStrb (EPP) / nAutoFd (SPP) Status bit for Active1284 (ECP) / Nastrb (EPP) / nSelectIn (SPP) Status bit for nReverseRequest (ECP) / nInit (EPP,SPP)
Notes: 1. Data written to bit 3-0 will be put on printer control bus if this device is in scanner mode. 2. When RD_PRINTER is low, reading bit 3-0 to reflect EPP HOST control signals.
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When RD_PRINTER is high, reading bit 3-0 to reflect the written data. 3. RD_PRINTER is bit 7 of address FFA0h. Parallel Port Host Data Register CPU Read/Write
Address: FFA2H Bit Reset Description 7 - 0 8'h00 When write, data will be put on parallel port data bus if DATA_OE = 1 (bit 7 of address FFA3h). When read, it reflects the data status in parallel port.
Parallel Port Device Status Register CPU Read/Write
Address: FFA3H Bit 7 Reset Description 0 Enable Parallel Port Reverse transfer. Data bus will be driven from Parallel Port Output Data register (address=FFA4h) to bus. (DATA_OE) 0: disable ; 1: enable Note: It is a necessary condition to output data before setting this bit to high, however, bit 3-0 of parallel port is also controlled by bit 7-4 of address FFA1h. Disable image_data_not_ready signal on UsrDf1 in hardware EPP mode. 0/1: enable / disable Reserved Device status : nPeripRqst (ECP) / UsrDf2 (EPP) / nFault (SPP) Device status : Xflag (ECP) / UsrDf3 (EPP) / Select (SPP) Device status : nAckReverse (ECP) / UsrDf1 (EPP) / Perror (SPP) Device status : PeripAck (ECP) / nWait (EPP) / Busy (SPP) Device status : PeripClk (ECP) / Intr (EPP) / nAck (SPP)
6
0
5 4 3 2 1 0
0 0 0 0 0 0
Notes: 1. Data written to bit 4-0 will be put on host parallel port (Excluding hardware control signals) 2. When RD_PRINTER is low, reading bit 4-0 to reflect written data. When RD_PRINTER is high, reading bit 4-0 to reflect PRINTER status signals. 3. RD_PRINTER is bit 7 of address FFA0h.
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EPP/USB DMA3 Start High Address Register CPU Read/Write
Address: FFA5H Bit Reset Description 7 - 0 00h For write, it is bit 15-8 of EPP DMA3 starting address. For read, it reflects the data of bit 15-8 of current counting address
EPP/USB DMA3 Start Low Address Register CPU Read/Write
Address: FFA6H Bit Reset Description 7 - 0 00h For write, it is bit 7-0 of EPP DMA3 starting address. For read, it reflects the data of bit 7-0 of counting address Note: It is up counter for DMA address.
EPP DMA3 Byte Count High Register CPU Read/Write
Address: FFA7H Bit Reset Description 7 - 0 00h The bit 15-8 of byte count for DMA3 transfer. (EPP only)
EPP DMA3 Byte Count Low Register CPU Read/Write
Address: FFA8H Bit Reset Description 7 - 0 00h The bit 7-0 of byte count for DMA3 transfer. (EPP only) Note: There will transfer n byte if byte count is programmed n
USB/EPP DMA3 Control Register CPU Read/Write
Address: FFA9H Bit Reset Description 7 - 5 111 Setup time to be added after receiving M22IP_ACK. Tsetup = Tcpu_period * bit[7:5] + Tnwait_to_dstrobe 4 0 USB transmit/receive target selection. 0: SRAM(M2) , 1:internal 8 bytes For internal 8 bytes RX/TX, index 0 register is first. 3 0 DMA3 read or write. 0: read; 1:write 2 1 1 0 EPP/USB selection for DMA3 transfer. 1: EPP mode; 0:USB mode DMA3 byte-count load. This bit will be self-cleared after loading byte count. For EPP mode, byte count will be loaded when writing "1" to this bit. For USB mode, byte count and packet count will be loaded when
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bit. After loading byte count, USB TX is enabled automatically. 0 0 Enable EPP DMA3 transfer. 0: disable; 1:enable. This bit will be cleared after finishing the DMA3 transfer. This bit is for EPP mode only.
Top Interrupt Status Register (1A -- with bit 7 of address FFB0h= 0) CPU Read/Write
Address: FFAAH Reset Description 0 Reserved 0 ECP send command event. 0:clear. Writing "1", the state is not changed. 5 0 EPP read address E4h event. 0:clear. Writing "1", the state is not changed. 4 0 EPP write address E4h event. 0:clear. Writing "1", the state is not changed. 3 0 DMA3 transmit done. 0: clear. Writing "1", the state is not changed. 2 0 DMA2 transmit done. 0:clear; Writing "1", the state is not changed. 1 0 Memory data overrun. 0:clear; Writing "1", the state is not changed. 0 0 Global USB interrupt event. 0 : clear ; 1 : set (read only) This bit reflects all the USB events. Note: These bits are set by event, and cleared by writing "0" to this bit
Top Interrupt Status Register (1B -- with bit 7 of address FFB0h= 1) CPU Read/Write
Bits 7 6
Address: FFAAH Bits Reset Description 7-1 0 Reserved 0 0 TG event. 0:clear; Writing "1", the state is not changed. Note: These bits are set by event, and cleared by writing "0" to this bit
USB Interrupt Status 2 Register CPU Read/Write
Address: FFABH Bits
7 6 5 4 3 2 1 0
Reset Description
0 0 0 0 0 0 0 0 NAK flag after USB EP2 RX done. 0: clear; Writing "1", the state is not changed. NAK flag after USB EP1 RX done. 0: clear; Writing "1", the state is not changed. NAK flag after USB EP0 RX done. 0: clear; Writing "1", the state is not changed. Detect USB Bus reset event. 0: clear; Writing "1", the state is not changed. This read-only bit reflects USB remote wake-up event (from device). Detect USB bus suspend event. 0: clear; Writing "1", the state is not changed. This read-only bit reflects USB bus resume event. Detect USB Start of Frame (SOF). 0: clear; Writing "1", the state is not changed.
Note: These bits are set by event, and cleared by writing "0" to this bit
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USB Interrupt Status Register (1A -- with bit 7 of address FFB0h= 0) CPU Read/Write
Address: FFACH
Bits Reset Description 7 0 Reserved 6 0 RX byte-count match event. 0: clear; Writing "1", the state is not changed. 5 0 USB EP2 RX Done. 0: clear; Writing "1", the state is not changed. 4 0 USB EP2 TX Done. 0: clear; Writing "1", the state is not changed. 3 0 USB EP1 RX Done. 0: clear; Writing "1", the state is not changed. 2 0 USB EP1 TX Done. 0: clear; Writing "1", the state is not changed. 1 0 USB EP0 RX Done (SETUP & OUT). 0: clear; Writing "1", the state is not changed. 0 0 USB EP0 TX Done. 0: clear; Writing "1", the state is not changed. USB Interrupt Status Register (1B -- with bit 7 of address FFB0h= 1) CPU Read/Write
Address: FFACH
Bits 7-6 5 4 3 2 Reset Description Reserved 0 USB TX under-run error. 0: clear; Writing "1", the state is not changed. 0 OUT data toggle bit error for EP2. 0: clear; Writing "1", the state is not changed. 0 0 (OUT-DATAx-ACK//OUT-DATAx-ACK, HUB doesn't receive ACK) TX data toggle bit error for EP1. 0: clear; Writing "1", the state is not changed. (IN-DATA-no ACK from HUB) TX data toggle bit error for EP0. 0: clear; Writing "1", the state is not changed.
(IN-DATA-no ACK from HUB) 1 0 USB EP0 RX Done for OUT. 0: clear; Writing "1", the state is not changed. 0 0 USB EP0 RX Done for SETUP. 0: clear; Writing "1", the state is not changed. Top Interrupt Enable Register (1A -- with bit 7 of address FFB0h= 0) CPU Read/Write
Address: FFADH
Bits Reset Description 7 0 Global Enable Interrupt for peripheral module. 0: disable ; 1:enable 6 0 Enable interrupt for ECP host send-command. 0:disable; 1:enable 5 0 Enable interrupt for EPP read address E4h event. 0:disable. 1:enable 4 0 Enable interrupt for EPP write address E4h event. 0:disable. 1:enable 3 0 Enable Interrupt for detecting DMA3 TX done. 0: disable ; 1: enable 2 0 Enable Interrupt for detecting DMA2 TX done. 0:disable ; 1:enable 1 0 Enable Interrupt for detecting memory overrun. 0:disable ; 1:enable 0 0 Enable Interrupt for global USB event. 0 : disable ; 1 : enable Top Interrupt Enable Register (1B -- with bit 7 of address FFB0h= 1)
CPU Read/Write
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Address: FFADH Bits 7-1 1 0 Reset Description 0 0 0 Reserved Select TG event. 0: /INT0 1: /INT1 Enable TG event. 0 : disable ; 1 : enable
USB Interrupt Enable 2 Register CPU Read/Write
Address: FFAEH
Bits Reset Description 7 0 Enable NAK for detecting USB EP2 RX done. 0:disable ; 1:enable 6 0 Enable NAK for detecting USB EP1 RX done. 0:disable ; 1:enable 5 0 Enable NAK for detecting USB EP0 RX done. 0:disable ; 1:enable 4 0 Enable Interrupt for detecting USB bus reset event. 0 : disable ; 1 : enable 3 0 Enable Interrupt for detecting USB remote wake-up event. 0 : disable ; 1 : enable 2 0 Enable Interrupt for detecting USB bus suspend event. 0 : disable ; 1 : enable 1 0 Enable Interrupt for detecting USB bus resume event. 0 : disable ; 1 : enable 0 0 Enable Interrupt for detecting USB Start of Frame (SOF). 0 : disable ; 1 : enable USB Interrupt Enable Register (1A -- with bit 7 of FFB0h= 0) CPU Read/Write
Address: FFAFH
Bits 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Description Reserved Enable RX byte-count match event. 0:disable; 1: enable Enable Interrupt for USB EP2 RX Done. 0 : disable ; 1 : enable Enable Interrupt for USB EP2 TX Done. 0 : disable ; 1 : enable Enable Interrupt for USB EP1 RX Done. 0 : disable ; 1 : enable Enable Interrupt for USB EP1 TX Done. 0 : disable ; 1 : enable Enable Interrupt for USB EP0 RX Done. 0 : disable ; 1 : enable Enable Interrupt for USB EP0 TX Done. 0 : disable ; 1 : enable
USB Interrupt Enable Register (1B -- with bit 7 of FFB0h= 1) CPU Read/Write
Address: FFAFH
Bits 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Description Enable NAK for USB EP2 RX data-toggle error. 0: disable; 1:enable Enable NAK for USB EP1/EP0 TX data-toggle error. 0: disable; 1:enable Enable Interrupt for USB TX under-run error. 0:disable; 1:enable Enable Interrupt for USB EP2 OUT data-toggle error. 0: disable; 1:enable Enable Interrupt for USB EP1 TX data-toggle error. 0: disable; 1:enable Enable Interrupt for USB EP0 TX data-toggle error. 0: disable; 1:enable Enable Interrupt for USB EP0 RX Done for OUT. 0: disable; 1:enable Enable Interrupt for USB EP0 RX Done for SETUP. 0: disable; 1:enable
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Interrupt Select Register CPU Read/Write
Address: FFB0H
Bits 7 Reset 0 Description Select USB interrupt enable register or USB interrupt status register to read or write. 0: USB interrupt status register 1A and USB interrupt enable register 1A 0: USB interrupt status register 1B and USB interrupt enable register 1B 6 0 Select ECP-host send-command event. 0: /INT0 1: /INT1 5 0 Select EPP read address E4h event. 0: /INT0. 1: /INT1 4 0 Select EPP write address E4h event. 0: /INT0. 1: /INT1 3 0 Select Interrupt for detecting DMA3 TX done. 0: /INT0 ; 1: /INT1 2 0 Select Interrupt for detecting DMA2 TX done. 0: /INT0 ; 1: /INT1 1 0 Select Interrupt for detecting memory overrun. 0: /INT0 ; 1: /INT1 0 0 Select Interrupt for all USB events. 0: /INT0 ; 1: /INT1 Device Flag Register CPU Read/Write
Address: FFB1H
Bit 7-0 Reset Description When write: The CPU written data will be latched in buffer, and can be read from EPP Host with E4h address. The default value is 8'h00 When read: The data comes from EPP Host port E4h (Host Access Device Flag Register) DMA3 Byte Count Auto-Reload Control Register CPU Read/Write
Address: FFB2H
Bit 7-5 4 3 2 1 Reset 0 0 0 0 Description Reserved Enable DMA counting value to be read. 0/1: disable/enable Flush USB TX prefetch-buffer. 0/1: disable/enable Force USB TX to be stopped. 0/1 : normal / stop Load TX packet count automatically when packet counter reaches zero (for USB) When this bit is set, USB TX data is always enabled until this bit is cleared by CPU. 0/1:disable /enable 0 0 Load DMA3 byte count automatically when counter reaches zero (for EPP) When this bit is enabled, DMA3 is not disabled by hardware, it must be cleared by firmware. 0/1:disable /enable USB Received Byte Count Low Register CPU Read/Write
Address: FFB3H Bits Reset Description
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7-0
8'b0 The bit 7-0 of byte count of received data
USB Received Byte Count High Register CPU Read/Write
Address: FFB4H
Bits Reset Description 7-5 Reserved 4-0 5'b0 The bit 12-8 of byte count of received data USB Received Byte Count Low Register to Generate Interrupt CPU Read/Write
Address: FFB5H
Bits Reset Description 7-0 8'b0 The bit 7-0 of byte count of USB RX data to generate interrupt USB Received Byte Count High Register to Generate Interrupt
CPU Read/Write
Address: FFB6H
Bits Reset Description 7-5 3'b0 Reserved 4-0 5'b0 The bit 12-8 of byte count of USB RX data to generate interrupt USB Request Type Register (USB setup command)
CPU Read Only
Address: FFB8H Bit 7-0 Reset Description 0 BmRequestType (offset=0 in SETUP command). Write from USB, Read from CPU
USB Request Code Register (USB setup command)
CPU Read Only
Address: FFB9H Bit 7-0 Reset 0 Description Brequest (offset=1 in SETUP command). Write from USB, Read from CPU
USB Request Value Low Byte Register (USB setup command)
CPU Read Only
Address: FFBAH Bit Reset Description
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7-0 0 Wvalue (low byte, offset=2 in SETUP command). Write from USB, Read from CPU
USB Request Value High Byte Register (USB setup command) CPU Read Only
Address: FFBBH Bit 7-0 Reset 0 Description Wvalue (high byte, offset=3 in SETUP command). Write from USB, Read from CPU
USB Request Index Low Byte Register (USB setup command) CPU Read Only
Address: FFBCH Bit 7-0 Reset 0 Description Windex (low byte, offset=4 in SETUP command). Write from USB, Read from CPU
USB Request Index High Byte Register (USB setup command) CPU Read Only
Address: FFBDH Bit 7-0 Reset Description 0 Windex (high byte, offset=5 in SETUP command). Write from USB, Read from CPU
USB Request Length Low Byte Register (USB setup command) CPU Read Only
Address: FFBEH Bit 7-0 Reset 0 Description Wlength (low byte, offset=6 in SETUP command). Write from USB, Read from CPU
USB Request Length High Byte Register (USB setup command) CPU Read Onl y
Address: FFBFH Bit 7-0 Reset 0 Description Wlength (high byte, offset=7 in SETUP command). Write from USB, Read from CPU
USB Endpoint Index Register (USB setup command) CPU Read Only
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Address: FFC0H Bits 7-2 Reset Description 0 Reserved Endpoint index (EPIDX) Bit[1:0] 00 Endpoint 0 01 Endpoint 1 10 Endpoint 2 11 Reserved
1-0
2'b0
DMA3 USB Status Register CPU Read Only
Address: FFC1H Bits 7-2 1 0 Reset Description Reserved. Read as "0" This read-only bit reflects Image_not_rdy status This read-only bit reflects TX_NOT_RDY status
DMA3 USB TX Byte Count for Internal 8-byte Register CPU Read/Write
Address: FFC2H Bits 7 6-0 Reset Description 0 Reserved Byte_Cnt8[6:0]. This byte count value is used when bit 4 of address FFA9h is high.
DMA3 USB TX Packet Size 2 Register (1A -- with bit 7 of FFB0h= 0) CPU Read/Write
Address: FFC3H Bits 7-2 1-0 Reset Description 0 Reserved 0 USB_pkt_size[9:8]. Bit 9-8 of USB TX packet size
DMA3 USB TX Packet Size 1 Register (1A -- with bit 7 of FFB0h= 0) CPU Read/Write
Address: FFC4H Bits 7-0 Reset Description 0 USB_pkt_size[7:0]. Bit 7-0 of USB TX packet size
DMA3 Disable Counting Register 2 (1B -- with bit 7 of FFB0h= 1) CPU Read/Write
Address: FFC3H
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Bits 7 6 Reset Description 0 Enable to stop counting for DMA3 transfer. 0/1: disable/enable 0 Enable hardware to solve IN-DATA-time-out recover (packet size 64 only). 0/1: disable / enable 5 0 Enable 8-byte registers USB TX request. 0/1: disable / enable 4 Reserved 3 0 Disable M2 USB TX request. 0/1: enable / disable 2 Reserved 1-0 0 Stop_DMA3_Count[9:8]. Bit 9-8 of stop DMA3 transfer count. DMA3 Disable Counting Register 1 (1B -- with bit 7 of FFB0h= 1) CPU Read/Write
Address: FFC4H
Bits Reset Description 7-0 0 Stop_DMA3_Count[7:0]. Bit 7-0 of stop DMA3 transfer count. DMA3 USB TX Packet Count 2 Register CPU Read/Write
Address: FFC5H
Bits 7-0 Reset 0 Description For write: USB_pkt_count[15:8]. Bit 15-8 of USB TX packet count For read: When bit 4 of FFB2h is low, it reflects the written data of register When bit 4 of FFB2h is high, it reflects bit 15-8 of counting byte DMA3 USB TX Packet Count 1 Register CPU Read/Write
Address: FFC6H Bits 7-0 Reset 0 Description For write: USB_pkt_count[7:0]. Bit 7-0 of USB TX packet count For read: When bit 4 of FFB2h is low, it reflects the written data of register When bit 4 of FFB2h is high, it reflects bit 7-0 of counting byte
Note: The total TX byte count is Usb_pkt_count * USB_pkt_size. Interrupt will be generated after total TX Byte Count is reached.
DMA3 USB Receive Packet Size Register 1 (1A -- with bit 7 of FFB0h= 0) CPU Read/Write
Address: FFC7H DMA3 USB Receive packet size Register 1A (with bit 7 of FFB0h= 0): Address = FFC7 Bits Reset Description 7 - 0 8'b0 Packet size of current received packet
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USB Debug Register 1 (1B -- with bit 7 of FFB0h= 1) CPU Read/Write
Address: FFC7H
Bits Reset Description 7 0 Enable to detect OUT error protocol. 0/1: disable/enable 6 0 Enable to detect EP0 IN error protocol. 0/1: disable/enable 5 0 Enable to detect EP1 IN error protocol. 0/1: disable/enable 4-0 0 Reserved USB Endpoint Control Register CPU Read/Write Address: FFC8H EPIDX[1:0]=2b00,EPCON0; EPIDX[1:0]=2b01,EPCON1 EPIDX[1:0]=2b10,EPCON2 (selected by FFC0h) Bits 7 6 5 4 3 2 1 0 Reset 0 0 1 0 1 1 1 1 Description Stall Receive Endpoint (SRE): If this bit is set, this endpoint will stall OUT token. Stall Transmit Endpoint (STE): If this bit is set, this endpoint will stall IN token. Control Endpoint (CE): This bit is set for EP0 only. ISO: Isochronous transfer Receive Input Enable (RIE): When disabled, this endpoint returns a NAK to OUT token. Endpoint Receive Enable (RE): When disabled, the endpoint does not respond to OUT token. Transmit Output Enable (TOE): When disabled, the endpoint returns a NAK to IN token. Endpoint Transmit Enable (TE): When disabled, the endpoint does not respond to IN token. USB Endpoint Transmit Status Register CPU Read/Write
Address: FFC9H
EPIDX[1:0]=2b00,EP_TXST0 ; EPIDX[1:0]=2b01,EP_TXST1 EPIDX[1:0]=2b10,EP_TXST2 (selected by FFC0h) Bits 7 Reset Description 0 Transmit Sequence (TSEQ): This bit will be transmitted in the next PID and toggled on a valid ACK handshake. 6-3 2 1 3'b0 Reserved. "0" when read 0 Transmit Time-out (TOUT): This bit is set when time-out occurred. (no ACK after DATA phase) 0 Transmit Error (TERR): This bit is set when error occurred, or this endpoint responds NAK to IN token.
0
0
Transmit Acknowledge (TACK): When this bit is set, means the data transmission is completed and acknowledge successfully.
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USB Endpoint Receive Status Register CPU Read/Write
Address: FFCAH
EPIDX[1:0]=2b00,EP_RXST0; EPIDX[1:0]=2b01,EP_RXST1 EPIDX[1:0]=2b10,EP_RXST2 (selected by FFC0h) Bits 7 6 5-3 2 1 0 Reset 0 0 0 0 0 0 Description Receive Sequence Bit (RSEQ): When receiving endpoint sequence, this bit is set. Receive Setup Token (RSETUP): When receiving the SETUP token, this bit is set. Reserved Receive Time-out (ROUT): This bit is set when time-out occurred. (No DATA after OUT token) Receive Error (RERR): This bit is set when error occurred, or this endpoint responds NAK to OUT token. Receive Acknowledge (RACK): When this bit is set, means the data reception is completed and acknowledge successfully. USB Device Address Register CPU Read/Write
Address: FFCBH Bits 7 6-0 Reset Description 0 Reserved Device Address[6:0]. Address is programmed through the command 7'b0 received from EP0 during the enumeration stage.
USB Device Control Register CPU Read/Write
Address: FFCCH
Bits 7 6 5 Reset 0 0 0 Description USB bus will be forced to SE0 state if this bit and bit 5 are high. This state of this bit will be put on USB data bus when bit 5 is enabled. USB transceiver output enable. When this bit is set, transceiver output is forced to enable and bit 6 will be put on D+. This function is used to enumerate device insertion or remove .0 / 1: disable / enable 4-3 2 0 0 Reserved Enable suspend/resume timer to detect suspend/resume event in USB bus 0 : disable ; 1 : enable
1 1 Enable reset timer to detect reset event in USB bus. 0 : disable ; 1 : enable 0 0 Put transceiver in power down mode. 0 : normal mode ; 1 : power down mode USB Device Status Tr ansmit Register 0 (DSTR0) CPU Read/Write
Address: FFD0H Bits Reset Description
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7-0 0 DSTR0[7:0] USB Device Status Transmit Register 1 (DSTR1) CPU Read/Write Address: FFD1H Bits Reset Description 7-0 0 DSTR1[7:0] USB Device Status Transmit Register 2 (DSTR2) CPU Read/Write Address: FFD2H Bits 7-0 Reset Description 0 DSTR2[7:0]
USB Device Status Transmit Register 3 (DSTR3) CPU Read/Write Address: FFD3H Bits 7-0 Reset Description 0 DSTR4[7:0]
USB Device Status Transmit Register 5 (DSTR5)
CPU Read/Write
Address: FFD5H Bits 7-0 Reset Description 0 DSTR5[7:0]
USB Device Status Transmit Register 6 (DSTR6)
CPU Read/Write
Address: FFD6H Bits 7-0 Reset Description 0 DSTR6[7:0]
USB Device Status Transmit Register 7 (DSTR7) 54
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CPU Read/Write
Address: FFD7H Bits 7-0 Reset Description 0 DSTR7[7:0]
Note: TX sequence is DSTR0 -> DSTR1 -> ... -> DSTR7
USB Device Command Receive Register 0 (DCRR0) CPU Read Only
Address: FFD8H Bits Reset 7-0 0 DCRR0[7:0] Description
USB Device Command Receive Register 1 (DCRR1)
CPU Read Only
Address: FFD9H Bits 7-0 Reset 0 DCRR1[7:0] Description
USB Device Command Receive Register 2 (DCRR2)
CPU Read Only
Address: FFDAH Bits Reset 7-0 0 DCRR2[7:0] Description
USB Device Command Receive Register 3 (DCRR3)
CPU Read Only
Address: FFDBH Bits 7-0 Reset Description 0 DCRR3[7:0]
USB Device Command Receive Register 4 (DCRR4)
CPU Read Only
Address: FFDCH Bits 7-0 Reset Description 0 DCRR4[7:0]
USB Device Command Receive Register 5 (DCRR5) CPU Read Only 55
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Address: FFDDH Bits 7-0 Reset Description 0 DCRR5[7:0]
USB Device Command Receive Register 6 (DCRR6)
CPU Read Only
Address: FFDEH Bits 7-0 Reset Description 0 DCRR6[7:0]
USB Device Command Receive Register 7 (DCRR7)
CPU Read Only
Address: FFDFH Bits 7-0 Reset Description 0 DCRR7[7:0]
Note: Receive sequence is DCRR0 -> DCRR1 -> ... -> DCRR7
The program memory can be read or written through EPP host, however, the procedure must be followed. The summary is listed as below. 1. Write Procedure: (a) Writing high address index by software ( nAStrb, high address index) (b) Writing high address data by software ( nDStrb, high address data) (c) Writing low address index by software ( nAStrb , low address index) (d) Writing low address data by software ( nDStrb , low address data) (e) Writing data index by software ( nAStrb , data index) (f) Writing data by software ( nDStrb , data) (g) Writing control register to request transfer, and ACK is cleared by hardware (h) Writing data to program memory by hardware (i) ACK bit is set by hardware, REQUEST is cleared by hardware 2. Read Procedure: (a) Writing high address index by software ( nAStrb , high address index) (b) Writing high address data by software ( nDStrb , high address data) (c) Writing low address index by software ( nAStrb , low address index) (d) Writing low address data by software ( nDStrb , low address data) (e) Writing control register to request transfer by software, and ACK is cleared by hardware (f) Reading data from program memory by hardware (g) ACK bit is set by hardware, REQUEST is cleared by hardware (h) Writing data index by software ( nAStrb , data index) (i) Reading data by software ( nDStrb , data)
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There are three special modes defined in GT6816. The first one is protect mode, it defines the mode which program can be read or written by EPP host. The second one is release mode, it defines the end of program memory can be accessed by EPP host. The protect mode and release modes are used to start and end of accessing program memory. The last one is scanner mode, it defines the signals from EPP host will be passed to printer chain or not? By sampling the data on the EPP host data bus, these three modes will be detected. These special sequences are defined in 32 bytes consecutive data. The detail codes for these three modes are listed as below. PROTECT 1. 01010101 (55H) 2. 01011101 (5DH) 3. 01111101 (7DH) 4. 01111111 (7FH) 5. 11111111 (FFH) 6. 11111110 (FEH) 7. 11101110 (EEH) 8. 11100110 (E6H) 9. 10100110 (A6H) 10. 10100010 (A2H) 11. 00100010 (22H) 12. 00100000 (20H) 13. 00000000 (00H) 14. 00000001 (01H) 15. 10000001 (81H) 16. 10000011 (83H) 17. 11000011 (C3H) 18. 11001011 (CBH) 19. 01001011 (4BH) 20. 01001010 (4AH) 21. 01101010 (6AH) 22. 01101000 (68H) 23. 01111000 (78H) 24. 01111001 (79H) 25. 11111001 (F9H) 26. 11111101 (FDH) 27. 11011101 (DDH) 28. 11010101 (D5H) 29. 10010101 (95H) RELEASE 01010101 (55H) 01011101 (5DH) 01111101 (7DH) 01111111 (7FH) 11111111 (FFH) 11111110 (FEH) 11101110 (EEH) 11100110 (E6H) 10100110 (A6H) 10100010 (A2H) 00100010 (22H) 00100000 (20H) 00000000 (00H) 00000001 (01H) 10000001 (81H) 10000011 (83H) 11000011 (C3H) 11001011 (CBH) 01001011 (4BH) 01001010 (4AH) 01101010 (6AH) 01101000 (68H) 01111000 (78H) 01111001 (79H) 11111001 (F9H) 11111101 (FDH) 11011101 (DDH) 11010101 (D5H) 10010101 (95H) SCANNER MODE 01010101 (55H) 01011101 (5DH) 01111101 (7DH) 01111111 (7FH) 11111111 (FFH) 11111110 (FEH) 11101110 (EEH) 11100110 (E6H) 10100110 (A6H) 10100010 (A2H) 00100010 (22H) 00100000 (20H) 00000000 (00H) 00000001 (01H) 10000001 (81H) 10000011 (83H) 11000011 (C3H) 11001011 (CBH) 01001011 (4BH) 01001010 (4AH) 01101010 (6AH) 01101000 (68H) 01111000 (78H) 01111001 (79H) 11111001 (F9H) 11111101 (FDH) 11011101 (DDH) 11010101 (D5H) 10010101 (95H)
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30. 10010100 (94H) 31. 00010100 (14H) 32. 00011100 (1CH) 1. USB Overview The USB hardware includes a USB function with one upstream port. The USB port interfaces to the micro-controller through a high-speed serial interface engine (SIE). This micro-controller provides the functionality of standard USB commands and scanner commands. 1-1 USB Serial Interface Engine (SIE) In order to allow the micro-controller to communicate with the USB host. The SIE handles the following USB bus activity: (a) NRZI decode / encode (b) Bit stuffing / un-stuffing (c) Checksum generation and checking (d) Address checking (e) Token type identification (f) Time-out check Firmware is required to handle the rest of USB interface: (a) Flow of USB bus enumeration (b) Function of USB standard commands (c) Function of scanner commands (d) Data transfer from buffer to USB host (e) Down-load program code from USB host 1-2 USB Enumeration The enumeration sequence is the process that the USB host uses to identify and manage the state of device when a USB device is attached to or removed from the USB. When a USB device is attached, the following actions are undertaken from device side: (a) USB host sends RESET command (b) USB host sends SETUP command with address 0 to get device descriptor (c) After receiving device descriptor, USB host sends SETUP command with new address to device (d) Device must store the new address after receiving the SETUP command (e) The host sends SETUP command with new address to get device descriptor (f) The host sends SETUP command to get configuration descriptor or other descriptor (g) Enumeration is complete after the host has received all the descriptor 1-3. Control pipe (Endpoint 0) Endpoint 0 is a bi-direction USB control endpoint. The USB host sends SETUP command to device through endpoint 0, this 8-byte command will be stored at GT6816 internal buffers which can be read by micro-controller from address FFB8H to FFBFH. The micro-controller must read command and interpret 10010100 (94H) 00010100 (14H) 00010101 (15H) 10010100 (94H) 00010100 (14H) 00111100 (3CH)
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command, and then handle the request from USB host. Both the USB standard commands and vendor-specific commands are through endpoint 0. 1-4. Image Line Buffer Read Pipe (Endpoint 1) Endpoint 1 is a USB BULK-IN pipe that transmits each packet of 64 bytes. This endpoint is used to send image data from buffer to USB host. The total packet count to be transmitted is depended on the DMA3 USB TX Packet Count 2 Register (FFC5H), DMA3 USB TX Packet Count 1 Register (FFC6H) and DMA3 Byte Count Auto-Reload Control Register (FFB2H). 1-5. Host Data Write Pipe (Endpoint 2) Endpoint 2 is a USB BULK-OUT pipe that receives packet up to 64 bytes in length. The received data can be written to image line buffer, the beginning address is specified in the EPP/USB DMA3 Start High Address Register (FFA5H) and EPP/USB DMA3 Start Low Address Register (FFA6H). The interrupt can be generated for each OUT transaction or last OUT transaction, it is easier for firmware to handle large data transfer.
VII. System Block Diagram
1. 16-bits Analog Front End(AFE) The Gain through each channel can be set between 0.8x and 7.8x. The Offset provides up to +/1.5V of offset correction. The gain and offset stages should be adjusted during coarse calibration so that input signal is a maximum of ? at the ADC input. The digital data comes from a 6 MHz 16-bit pipelined ADC. The output data is formatted as a 16 bit word.
2. Clock source GT6816 uses 6MHz external crystal as the input clock. Typically when PPLL_EN_ is pull to low, internal built-in PLL is enable and output 48MHz as the master clock to eliminate EMI effects. As PPLL_EN_ is pull to high, PLL is disabled and external crystal output is directly sent to internal as the master clock. In this mode, always use 48MHz crystal as the input clock source.
3. External Serial EEPROM interface GT6816 support I2C serial EEPROM interface for updating program code on the power-on state. GT6816 searches the external serial EEPROM on the power-on state. If no serial EEPROM is present, embedded program code will be used. This is helpful when system is on the developing state. Note that always pull high on SCL and SDA pin.
4. DMA transfer There are 3 DMA transfers on GT6816. (i) DMA1:
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DMA1 is defined for transferring data from M2 (image buffer) to M1 (program memory). When DMA1 is active, CPU enters the suspend-state and waits for the end of DMA1. The total bytes of DMA1 transfer and the target address of M1 can be programmed. After DMA1 is complete, CPU leaves suspend-state and operates with newly updated program code. It is helpful for updating firmware stored in M1 and implement different function. PC can load the new code to M2 via DMA3 write operation and request CPU to do DMA1 transfer. On this concept, any changes of firmware version can be easily updated via Internet. (ii) DMA2 The sensor analog input is sent to 16-bits AFE and output digital pixel data to M2. This process is called DMA2. Each DMA2 is synchronized with TG signal and generates end of DMA2 event to CPU. While end of DMA event occurs, CPU checks the image buffer status to determine whether to continue DMA2 or not. (iii) DMA3:
PC interface read/write M2 is the process of DMA3
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5. Built-in 16K image buffer GT6816 uses internal 16K SRAM as the image buffer to store the pixel data via DMA2 process and send it to PC interface via DMA3. The purpose of image buffer is used as the buffer between DMA2 and DMA3. For the fast DMA3 (PC interface read from buffer), image buffer is never full and has a best performance on the pixel data transfer. If DMA3 is slower, as the buffer is near full, DMA2 (pixel data write to buffer) will be halted and wait for enough buffer size to continue. Built-in image buffer ,therefore, can save the external memory requirement.
6. Watch dog timer GT6816 has built-in watch-dog-timer to avoid uncertain conditions that make CPU reach unknown state. CPU has to reset the watch-dog-timer every 500ms. If CPU does not reset watch-dog-timer more than 500ms, GT6816 will return initial state and reset all the hardware settings.
7.Remote-wake up function Change states on pin WAKEUP will force GT6816 leave suspend state and do the corresponding service. 8. Programmable timing generator All sensor and AFE control signals can be fully programmable by timing generator module. This provides the highly compatibility to the different system requirements. 9. Suspend management Each module include AFE, CPU, program memory, image buffer, DMA controller, etc, has its corresponding suspend control bit. Entering suspend state is determined by CPU setting these bits. That makes bus-powered of USB solution can be easily implemented.
10.
General-purpose I/O There are up to 42 pin GPIO in 128-pin package.
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VIII. APPENDIX: PACKAGE MECHANICAL DATA- 128-pin QFP
A D D1
102 65
A2
A1 D y
103
64
E
E1
128
39
1
38
e
B
c
GAGE PLANE
0.25
L
Symbol Dimensions in inch Min. 0.010 0.107 0.007 0.004 0.906 0.783 0.669 0.547 0.029 0 Nom. 0.112 0.009 0.913 0.787 0.677 0.551 0.020 BSC 0.035 0.063 BSC 0.004 7 0.041 Max. 0.134 0.117 0.011 0.008 0.921 0.791 0.685 0.555
Dimensions in mm Min. 0.25 2.73 0.17 0.09 23.00 19.90 17.00 13.90 0.73 0 Nom. 2.85 0.22 23.20 20.20 17.20 14.00 0.5 BSC 0.88 1.60 BSC 0.10 7 1.03 Max. 3.40 2.97 0.27 0.20 23.40 20.10 17.40 14.10
A A1 A2 B C D D1 E E1 e L L1 y
Notes: 1. Dimensions D1 and E1 do not include mold protrusion. But mold mismatch is included. Allowable protrusion is .25mm/.010" per side. 2. Dimensions B does not include dambar protrusion. Allowable dambar protrusion is .08mm/.003"" per side. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
L1
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q This publication contains the design target or goal specifications for product development. Specifications and information herein are subject to change without prior notice. q All Copyrights are reserved: No part of this publication may be reproduced or duplicate in any form or by any means without the prior written permission of Grandtech Semiconductor Corp. q All applications and circuit parameters herein are for illustrative purposes only. Grandtech Semiconductor makes no warranty that such applications will be suitable for volume production without further testing or modification. q Grandtech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life.
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